Virage Logic Corporation reported unaudited consolidated earnings results for the fourth quarter and full year ended September 30, 2009. For the quarter, total revenues were $13,148,000 against $15,513,000 a year ago. Operating loss was $5,711,000 against $1,058,000 a year ago. Loss before taxes was $5,727,000 against $303,000 a year ago. Net loss was $3,244,000 or $0.14 per basic and diluted share against $47,000 or $0.00 per basic and diluted share a year ago. Non-GAAP net income was $489,000 or $0.02 per basic and diluted share. For the year, total revenues were $47,443,000 against $59,330,000 a year ago. Operating loss was $29,346,000 against $2,948,000 a year ago. Loss before taxes was $28,672,000 against income before taxes of $447,000 a year ago. Net loss was $34,124,000 or $1.48 per basic and diluted share against net income of $554,000 or $0.02 per basic and diluted share a year ago. Non-GAAP net loss was $3,390,000 or $0.15 per basic and diluted share a year ago. For the first quarter of fiscal 2010, the company expects to report revenues of $18.5 million to $19.0 million and non-GAAP EPS results of $0.02 to $0.04. The company expects to realize, before tax, approximately $2.6 million to $2.8 million in non-GAAP adjustments comprised primarily of stock-compensation and acquisition-related expenses.

Virage Logic Corporation expected to Report Q1 2010 Results on January 25, 2010. This event was calculated by Capital IQ (Created on November 2, 2009).

Open-Silicon Inc., MIPS Technologies Inc. and Virage Logic Corporation announced the co-development of test chips showcasing the companies' technologies for building high-performance processor-based systems. The companies achieved successful 65 nanometer (nm) silicon testing of a processor test chip at 1.1GHz, making it one of the processors built in a 65nm ASIC. Also, work has begun on a follow-on 40nm device targeting frequencies in excess of 2.5GHz and providing over 5000 DMIPS of performance. Both efforts utilize Open-Silicon's CoreMAX(TM) technology as well as the superscalar MIPS32® 74K® processor core, a fully synthesizable processor core widely used in high-end digital consumer devices, set top boxes, and networking solutions. The 65nm test chip was designed to show how the companies' technologies can be used to achieve top performance in a standard ASIC implementation. The 74K processor core is complemented with 32KB L1 instruction and data caches, a 512KB L2 cache, and system and memory controller blocks, and was implemented using TSMC's 65nm GP process with standard 10 track libraries and Virage Logic's SiWare(TM) Memory compilers. The companies have working silicon running at 1.1 GHz. To achieve this goal, Open-Silicon applied its patented CoreMAX performance enhancement technology to the design. This technology permitted the designers to build several hundred new standard cells targeted specifically at speeding up the design's critical paths. This, along with the advanced SiWare Memory compilers and a triple Vt process option, allowed final design worst-case timing closure across all corners at 1.1GHz with standard ASIC margins.