Synopsys Unveils 30 Percent Smaller Area, Low Power USB 2.0 PHY IP for 28-nm Processes

MOUNTAIN VIEW, Calif., Oct. 29 /PRNewswire-FirstCall/ -- Synopsys, Inc. (Nasdaq: SNPS - News), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced the addition of the new DesignWare® USB 2.0 picoPHY IP to its USB 2.0 PHY IP product line that has been successfully deployed in more than 300 customer designs, and in more than 50 different process technologies ranging from 180-nanometer (nm) to 32-nm. Targeted at mobile and high-volume consumer applications such as feature-rich smartphones, mobile internet devices and netbooks, the DesignWare USB 2.0 picoPHY supports advanced 28-nm processes in a 1.8V architecture, is 30 percent smaller than the previous USB 2.0 PHY generation, and offers reduced pin count and low standby power consumption. The DesignWare USB 2.0 picoPHY IP is the first PHY IP to support the new Battery Charging version 1.1 and USB On-the-Go (OTG) version 2.0 specifications from the USB Implementer's Forum (USB-IF). The Battery Charging v 1.1 specification allows mobile devices to draw up to 1.8 A of current when connected to a wall charger. The Battery Charging specification enables portable devices to distinguish among various power sources, such as a wall charger, standard host port and USB charging port, and selects the most efficient method to charge the device. By supporting the USB OTG version 2.0 specification, the DesignWare USB 2.0 picoPHY incorporates the new Attached Detection Protocol (ADP) feature, which improves the power efficiency of portable d...
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NVIDIA Adopts Synopsys Yield Explorer to Reduce Time to Volume

MOUNTAIN VIEW, Calif., Oct. 28 /PRNewswire-FirstCall/ -- Synopsys, Inc. (Nasdaq: SNPS - News), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that NVIDIA Corp., has adopted Synopsys' Yield Explorer solution for yield analysis and yield ramp. NVIDIA, which invented the graphics processing unit, selected Yield Explorer because of its ability to coherently combine and cross-correlate large volumes of data from the design, fab and test domains to quickly identify dominant failure mechanisms. This is accomplished through volume diagnostics based on TetraMAX® ATPG and other advanced analysis applications. "At NVIDIA, we face an increasingly challenging production ramp at each successive nanometer node," said Bruce Cory, manager DFx technology at NVIDIA. "We selected Yield Explorer because this solution has all the traditional yield analysis features combined with unique design-centric, volume diagnostics capabilities. Yield Explorer was able to handle gigabytes of data per day from the test floor and combine it with the design and fab data."Ramping new devices to volume production with good yield has evolved into a complex multi-dimensional project at nanometer nodes. On one hand, technical teams must rely on thorough characterization of new devices to set up effective testing, monitoring, control and root-cause analysis flows. On the other, operational efforts require careful and thorough trimming of these flows to optimize yield management at the lowest cost. The ke...
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Synopsys Extends DFTMAX Compression to Reduce the Cost of Pin-Limited Test

MOUNTAIN VIEW, Calif., Nov. 2 /PRNewswire-FirstCall/ -- Synopsys, Inc. (Nasdaq: SNPS - News), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced a new capability in DFTMAX(TM) compression that significantly reduces the cost of test for designs and methodologies that mandate very few test pins. Extending Synopsys' patented adaptive scan technology with a high-performance, low-pin interface to the tester allows designers to achieve predictable compression of up to 100X or more with only one pair of test data pins. As designers must maintain test quality and reduce test cost while design complexity is growing, they increasingly adopt core-based design and test methodologies as well as multi-site testing techniques, significantly limiting the number of pins allocated for test. Widely deployed, DFTMAX compression now delivers even greater test time and cost savings for today's challenging designs. "Timely delivery of highly reliable products to our customers is essential for our success," said Jean-Louis Cols, vice president of product development at Wolfson Microelectronics. "To meet our quality goals and lower the cost of production testing, we continually strive to maximize test coverage and minimize test data volume and test time whilst considering the capabilities and limitations of the target tester platform. DFTMAX compression and TetraMAX® ATPG have repeatedly allowed us to achieve these goals for our latest mixed-signal designs. The new enhancements in DFTMAX compressi...
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Juniper Chooses Synopsys as Its Primary EDA Partner

MOUNTAIN VIEW, Calif., Oct. 30 /PRNewswire-FirstCall/ -- Synopsys, Inc. (Nasdaq: SNPS - News), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that Juniper Networks has signed a multi-year business agreement establishing Synopsys as its primary EDA partner. Under the new agreement, Juniper will use Synopsys' Galaxy(TM) Implementation and Discovery(TM) Verification Platforms to meet their expanding chip development needs. "Synopsys has played a key role in helping us execute on our broad open foundry strategy, including the successful migration of some of our leading designs to advanced process nodes," said R.K. Anand, executive vice president of Foundation Technologies at Juniper Networks. "Most recently, with the help of tools from Synopsys we were able to design and bring to market our latest Junos® Trio chipset that enables the delivery of Juniper's MX-3D platforms. By deepening our collaboration with Synopsys, we can continue to deliver on the promise of a connected world through leadership in both silicon design and high performance network architecture."This latest agreement between the two companies expands Juniper's use of Synopsys' extensive portfolio of products and consulting services. These products include the Synopsys Galaxy(TM) Implementation Platform's IC Compiler place-and-route technology, Design Compiler® Ultra synthesis, Formality® power-aware equivalence checking, DFT Compiler, PrimeTime® SI signal integrity analysis, and StarRC(...
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Synopsys TetraMAX ATPG Cuts Test Development Schedule at Arrow Electronics

MOUNTAIN VIEW, Calif., Nov. 3 /PRNewswire-FirstCall/ -- Synopsys, Inc. (Nasdaq: SNPS - News), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that Arrow Electronics successfully deployed Synopsys' TetraMAX® automatic test pattern generation (ATPG) with multicore processing to significantly reduce the time needed to generate high-quality manufacturing tests. Stringent quality goals combined with increasing design complexity stimulated the need to improve ATPG performance at Arrow. By utilizing TetraMAX ATPG's multicore processing capability on their quad-core compute servers, Arrow's Custom Logic Solution (CLS) ASIC design engineers cut more than a week from their test development time for a 30 million-gate system-on-chip, meeting their test quality goals ahead of schedule. "To meet Arrow's quality goals, our CLS ASIC designers rely on at-speed manufacturing tests that can take days to generate," said Erich Van Stralen, ASIC test team manager at Arrow Electronics. "For our latest project, we used TetraMAX ATPG running on quad-core machines, which reduced test pattern generation time to less than 24 hours with no impact on fault coverage. We now consider the Synopsys multicore ATPG capability essential to meeting our quality goals on time."Generating deep-submicron tests on a single processor core can take weeks or longer, especially for very large designs. TetraMAX's multicore processing capability employs algorithms to ensure that runtime performance scales well...
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Media Advisory/Alert: Synopsys EDA Interoperability Forum to Feature Subodh Bapat Keynote on Green Computing

MOUNTAIN VIEW, Calif., Nov. 2 /PRNewswire-FirstCall/ -- Synopsys, Inc. (Nasdaq: SNPS - News), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that its 22nd electronic design automation (EDA) Interoperability Forum will feature keynote speaker Subodh Bapat, vice president, energy efficiency and distinguished engineer at Sun Microsystems, on the topic of "Groovy Green Computing: Battling the Mushrooming Use of Power." WHO: The event is recommended for EDA tool developers, IC design engineers, and IP providers to discuss the industry-critical topics of interoperability and standards.WHAT: The November 2009 Forum focuses on the latest developments in EDA interoperability with sessions dedicated to:The Interoperable Process Design Kit (PDK) Libraries Alliance:System-Level Design:VMM Verification Methodology:The Forum, with this year's theme of "Peace, Love and Interoperability," also features the most recent advances in these key EDA standards: Liberty(TM) Library Modeling, IEEE Standard 1801(TM) for Low Power, and the HapsTrak(TM) standard for prototyping board connectors.WHEN: Thursday, November 5th in Santa Clara, Calif. The Forum is open to all who wish to attend at no cost. Lunch and a light breakfast are included.WHERE: The Sun Conference Center at Agnews Historic Park in Santa Clara, Calif. from 9:00am to 5:00pm. For more information, directions, and to register, visit: ...
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Synopsys Announces Earnings Release Date and Conference Call for Fourth Quarter and Fiscal Year 2009

MOUNTAIN VIEW, Calif., Nov. 11 /PRNewswire-FirstCall/ -- Synopsys, Inc. (Nasdaq: SNPS - News), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced it will report results for the fourth quarter and fiscal year 2009 on Wednesday, Dec. 2, 2009, after the market close. A conference call to review the results will begin at 2 p.m. PT (5 p.m. ET) and will be hosted by Aart de Geus, chairman and chief executive officer, and Brian Beattie, chief financial officer.Financial and other statistical information to be discussed on this conference call will be available on the corporate website at http://www.synopsys.com immediately before the call. A live webcast will also be available on this site. Participants should access the live webcast at least 10 minutes prior to the start of the call. A webcast replay can be accessed on the corporate website beginning Wednesday, Dec. 2, 2009, at approximately 5:30 p.m. PT. The replay will remain available until Synopsys announces its first quarter fiscal year 2010 results in February 2010. In addition, a dial-up replay of the conference call will be available beginning Dec. 2, 2009 at 4:00 p.m. PT, ending on Dec. 16, 2009 at midnight. The replay telephone number is USA (800) 475-6701, and International (320) 365-3844, Access Code: 122503....
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Synopsys Chosen by Realtek as Its Primary EDA Partner

MOUNTAIN VIEW, Calif., Nov. 5 /PRNewswire-FirstCall/ -- Synopsys, Inc. (Nasdaq: SNPS - News), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that Realtek Semiconductor Corp., a leading provider of advanced IC products for communications network, computer peripheral and multimedia applications, has signed an expanded business agreement establishing Synopsys as its primary EDA partner. Under the new multi-year agreement, Realtek has extended its use of Synopsys' Galaxy(TM) Implementation, Discovery(TM) Verification and Confirma(TM) Rapid Prototyping Platforms, as well as Synopsys' DesignWare® IP and consulting services. "By selecting Synopsys as our primary EDA partner, we are choosing more than tools, we are choosing a company that shares our commitment to creating differentiated system-on-chip solutions," said Alex Chiu, chief executive officer at Realtek. "Through years of cooperation and expanded use of Synopsys technology, we have demonstrated success in our ability to design high performance, energy-efficient products in a cost-effective manner. Going forward, we will continue to take advantage of Synopsys' technical leadership and world-class support to drive enhancements in design efficiency and accelerate new product development.""The rapid development and introduction of innovative chip-level solutions relies on expertise in multiple design domains and an understanding of the entire system, areas in which Realtek excels," said Chi-Foon Chan, president ...
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Digital Imaging Systems Achieves First-pass Silicon Success With Synopsys Galaxy Custom Designer

MOUNTAIN VIEW, Calif., Nov. 16 /PRNewswire-FirstCall/ -- Synopsys, Inc. (Nasdaq: SNPS - News), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that Digital Imaging Systems GmbH (DIS) has achieved first-pass silicon success using Synopsys' Galaxy Custom Designer(TM) implementation solution and its unified suite of circuit simulation, extraction and physical verification tools for a custom integrated circuit (IC) used in DIS' high-performance, multi-megapixel camera modules. The productivity enhancements afforded by Custom Designer, combined with its interoperable and open environment, enabled DIS to completely replace its existing flow and tape out a new IC design in under one month. "Smart phone customers demand the highest-quality images, so it is critical that we deliver camera modules early enough to be built into the next generation of phones," said Roland Pudelko, CEO at DIS. "Synopsys' Custom Designer, coupled with expert field support, provides the most productive and complete custom implementation solution needed to meet our customers' requirements on schedule."Product release cycles in the camera module market continue to shrink, and suppliers must keep pace with tight delivery schedules. DIS teamed with Synopsys to deploy Custom Designer to increase productivity and facilitate on-time delivery. Supported by Synopsys, DIS made a quick transition from their legacy point tool flow and proprietary databases, which helped them tape out ahead of schedule and achi...
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Synopsys Earnings Call scheduled for Wed, Dec 2

Call DetailsSynopsys Earnings Conference Call (Q4 2009)Scheduled to start Wed, Dec 2, 2009, 5:00 pm EasternAfter the event has finished, the audio will be availablefrom this page until Fri, Dec 3, 2010About Synopsys (NasdaqGS:SNPS)Synopsys, Inc. and its subsidiaries provide electronic design automation software and related services for semiconductor design companies in the United States, Europe, Japan, and the Asia Pacific. It delivers semiconductor design and verification and integrated circuit (IC) manufacturing software products to the electronics market; intellectual property (IP), system-level design hardware and software products, and design services; and software and services that help prepare and optimize designs for manufacturing. The company’s galaxy design platform includes Design Compiler, a logic synthesis product; Synplify synthesis product used to optimize designs of field programmable gate arrays; IC Compiler, a physical design solution; Galaxy Custom Designer, a physical design solution; PrimeTime, a timing analysis product; PrimeYield, a tool suite for manufacturing yield enhancement; Star-RCXT, an extraction solution for analyzing IC layout data; and Hercules, a physical verification product family. Its discovery verification platform comprises VCS, a register transfer level verification solution; Formality, a verification sign-off solution; NanoSim FastSPICE, a circuit simulation product; HSIM, a hierarchical FastSPICE circuit simulation product for analog, mixed-signal, and digital IC verification; and HSPICE, a circuit simulator product. The company also offers IP and system-level solutions that enable verification and embedded software development, as well as analog-to-digital converters, digital-to-analog converters, audio codecs, and power management. Its manufacturing solutions consist of Technology-CAD products, Pro...
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